1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device capable of restraining power supply voltage variation.
2. Description of the Related Art
With rapid progress of microtechnology, power consumption in the whole system tends to increase as the integration intensity of semiconductor integrated circuits increases in recent years. As the situation now stands, it has strongly been called for to lower power consumption in semiconductor integrated circuit devices
As the technology of reducing power consumption, it is an applicable one to control the supply of power to a plurality of blocks formed on one semiconductor chip. With the control of the supply of power to the plurality of blocks, however, there develops a demand for the technology of supplying power uniformly to each block by restraining variations in the block-to-block power supply potential. In this case, the block means an assembly of circuits such as a logic circuit and a memory array consisting of a plurality of logical elements or memory elements like flip-flops and having a fixed function.
As shown in FIG. 8, a conventional semiconductor integrated circuit device comprises a semiconductor chip 1001, a main system block 1022 around which power supply wiring is arranged, subsystem blocks 1023a and 1023b around which power supply wiring is also arranged, feeder terminals V1–V8, and switching elements S11–17 and S21–S24.
As shown in FIG. 9, each of the switching elements S11–17 and S21–24 is formed with P-type MOS transistors T1 and T2, resistors R1 and R2 and output terminals VDD0, VDD1 and VDD2.
In FIG. 8, power supply potential VDD is supplied via the switching elements S11–17 to the main system block 1022 formed on the semiconductor chip 1001 and the power supply potential VDD is supplied via the switching elements S21–24 to the subsystem block 1023b. 
For example, it is assumed that the P-type MOS transistor T1 that forms each of the switching elements S21–24 sets a threshold voltage for turning on/off the channel at 0.75 V as the voltage applied across the gate-source and that the P-type MOS transistor T2 that forms each of the switching elements S11–17 sets a threshold voltage for turning on/off the channel at 1.0 V as the voltage applied across the gate-source.
Assuming that the potential difference between the power supply potential VDD and the ground potential GND is 4 V at this time, the voltage across the gate-source of each of the P-type MOS transistors T1 and T2 comes to 1.0 V, which results in turning on the P-type MOS transistor T1 and turning off the P-type MOS transistor T2. Consequently, the power supply potential VDD is supplied to the subsystem blocks 1023a and 1023b, so that each block becomes operated. However, the power supply potential VDD is not supplied to the main system block 1022, so that the main system block 1022 becomes unoperated.
Assuming that the potential difference between the power supply potential VDD and the ground potential GND is 5 V, the voltage across the gate-source of each of the P-type MOS transistors T1 and T2 comes to 1.25 V, which results in turning on the P-type MOS transistors T1 and T2. Consequently, the power supply potential VDD is supplied to the main system block 1022 and the subsystem blocks 1023a and 1023b, so that each block is operated.
Thus, the operating or unoperating condition of each block has been controlled by changing the value of one kind of power supply potential VDD supplied from the outside to turn on/off the switching elements S1–S24 connected to the power supply wires 1022, 1023a and 1023b, whereby the power consumption has been decreased by operating only the required block (see JP-A-5-21713 (pp 3–4, FIGS. 3–4) 1, for example).
With the above conventional arrangement, the blocks 1022 and 1023b are supplied with power invariably from the feeder terminals V1–V8 via the switching elements S11–17 and S21–24.
Consequently, a voltage drop occurs because of the resistance of the switching elements S11–17 and S21–24 when the power supply potential VDD is supplied to the feeder terminals V1–V8. When the power supply potential reaches each block, it has VDD−α in the main system block 1022 and VDD−β(α≠β) in the subsystem block 1023b, for example, and as the power supply potential that reached the blocks attains different values, the problem in this case is that the block-to-block power supply potential tends to cause variation.
In order to reduce the voltage drop by means of the switching elements, it is needed to lower the resistance of the switching elements. Accordingly, a switching element formed with a P-type MOS transistor having a greater source-drain width has to be used and there is a problem arising from an increase in not only the size of the switching element but also the whole area of the semiconductor chip 100.